clock signal
英 [klɒk ˈsɪɡnəl]
美 [klɑːk ˈsɪɡnəl]
网络 时钟信号; 时脉信号; 时脉讯号; 时钟脉冲信号; 定时器讯号
双语例句
- C1E tries to provide more power savings than the traditional C1 state ( which only halts the clock signal) by also lowering the voltage and frequency.
同样通过降低电压和频率，C1E尝试比传统C1状态（只会停止时钟信号）提供更大的电能节省。 - Generation of Multi-Wavelength Optical Pulses and Electrical Clock Signal Utilizing Optoelectronic Oscillator with Single Light Source
利用单光源光电振荡器实现多波长光脉冲与电时钟信号产生 - The transition from voltage to no voltage is referred to as the trailing edge of a clock signal.
电感从一定值下降到0值的跃迁叫做时钟信号的后沿。 - All of the ports with APDs work on the time division and cooperate with a logic discriminating and deciding unit driven by the clock signal.
所有端口采用时分工作模式，系统时钟信号驱动逻辑鉴别与判决单元完成光-电信号的转换。 - In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.
在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。 - The clock signal is obtained by using a frequency doubler which uses a modified XOR topology, so that the complexity of the system is reduced.
改进异或门拓扑结构实现的二倍频器，结构简单、实用，降低了电路复杂度。 - In digital circuits, often requires a higher clock frequency sub-band operation, a lower frequency clock signal.
在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。 - Represents a crystal clock signal generator. Number of electrodes can be specified.
表示晶体时钟信号发生器。可指定电极数目。 - A clock signal with 1 million pulses per second is referred to as a 1 megahertz.
每秒钟有一百万个脉冲及时钟信号，也称兆赫。 - In this case, MCL is the memory clock signal, while MDA is the memory data signal.
在这种情况下，内侧副韧带是内存时钟信号，而MDA是内存数据信号。 - Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal.
它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。 - The principle of the method is to introduce a clock isolation circuit which tracks clock transitions just like a clock signal, yet isolates the clock from the "clock-used-as-data" logic.
主要的方式是导入时钟隔离电路追踪时钟转换如时钟讯号，然后“时钟做为资料”逻辑做为隔离时钟技术。 - The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。 - Data sent from the device to the host is read on the falling edge of the clock signal;
从设备发送给主机的数据时在时钟信号的下降沿读取的； - The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.
你的微型计算机执行程序的速度将与你的时钟信号的速度成线性关系。 - The latest three-phase clock signal control method was used to control the working state of charge pump.
电路采用了预启动和衬底电位选择结构，并利用三相时钟信号方式控制电荷泵的工作状态。 - The relationship between the clock jitter and the sampling sequence of a sine wave is studied, and a new method to measure the jitter and distribution of a clock signal with pico-second resolution is proposed using ADC sampling based on estimating method of the parameters in sine signal.
研究了时钟抖动与正弦信号的采样序列之间的关系，并在正弦信号参数估计法的基础上，提出一种利用ADC采样测量皮秒量级的时钟抖动大小和分布的新方法。 - To produce high speed, robust clock signal is the aim of this research.
生成高速，稳定的时钟信号是本课题的目标。 - In the process of implementation, not only FPGA's inner resources were fully made use of, but also the circuit mistakes caused by signals 'burrs were avoided using FPGA's inner clock signal to make the asynchronous signals synchronized.
系统在实现过程中，利用FPGA内部时钟信号clk同步化异步信号，不但充分发挥了FPGA的内部资源，且避免了因信号毛刺可能产生的电路错误。 - Based on analyzing the structure of civil digital walkie-talkie, this paper particularly introduces several key modules of the chip, such as microprocessor and interface 、 voice coding/ decoding module 、 base band and RF module 、 the clock signal.
在分析民用数字对讲机基本结构的基础上，本文对芯片设计的总体框架及某些关键模块如ARM微处理器和外围接口、语音编/解码模块、基带和射频模块、时钟信号设计等作了详细介绍。 - The paper discusses general expresses of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, the unified theory for designing and analysing both synchronous and asynchronous sequential circuits is proposed.
本文讨论了时钟信号的普遍描述和含时钟信号的触发器次态方程，并在此基础上提出了同步和异步时序电路的统一设计和分析理论。 - DS90CR213/ 214 receiver-transmitter used simple difference signal pair which included clock signal pair and three signal difference pair.
DS90CR213/214收发器采用特别简洁的差分信号对，包括时钟信号对和三对信号差分对。 - According to the adaptive control principle, output parameters of oven controlled crystal oscillator and the pulses per second ( PPS) signals of GPS are identified and processed by using the CPLD and single-chip microcomputer. Therefore, a high-precision sync clock signal with settable frequency is formed.
以“CPLD+单片机”作为控制器件，依据自适应控制的原理对恒温晶振的时钟信号和GPS的秒脉冲（pulsespersecond，PPS）进行参数辨识和自适应处理，获得了频率可设定的高精度同步时钟信号。 - By using real time clock chip ( DS1302) to produce clock signal.
采用实时时钟芯片（DS1302）产生时钟信号； - The clock signal with precise duty cycle produced by DCM is used in the bus data DDR transmission. The simulation results are also given.
利用DCM产生的具有精确占空比的时钟信号，给出了其在DDR总线数据传输中的应用，并给出了仿真结果。 - With further research, Modern High-energy physics experiments required precise and stable clock signal.
在大型现代高能物理实验中，随着研究目标的深入，对时钟信号的精度和稳定性提出了更高的要求。 - Clock tree is a transmission network of clock signal, which influence the function and performance of system.
时钟树作为时钟信号的传播网络，也就影响了芯片的功能和性能的优劣。 - The main chip control the clock signal of FPGA, the FPGA works in slave mode.
主芯片通过SSC接口与FPGA进行通信，控制FPGA的时钟信号，FPGA工作于从模式，控制FPGA的时钟信号。 - With the device complexity more and more, the sampling clock signal has been put forward higher requirements.
随着待测设备复杂性和工作频率的提高，对采样时钟信号提出了更高的要求。